1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device using a command control system.
2. Description of the Related Art
A flash EEPROM (Electrically Erasable programmable Read Only Memory) is one of nonvolatile memories that can be electrically written into and erased from. The configuration of a memory cell made up of a floating-gate MOS transistor in a flash EEPROM and general writing and erasing means will be described with reference to FIGS. 1 and 2.
FIG. 1 is a plan view of a memory cell portion of a floating-gate MOS transistor, and FIG. 2 is a sectional view taken along line 2--2 of FIG. 1. The floating gate MOS transistor contains a stacked gate electrode 506 composed of a thin gate insulating film 502 on a semiconductor substrate 501, a polysilicon floating gate 503 on the insulating film, a gate insulating film 504 on the gate, and a polysilicon control gate 505 on the insulating film 504. By implanting ions using the gate electrode 506 as a mask, a source diffused layer 507 and a drain diffused layer 508 are formed at the surface of the substrate 501. Numeral 509 indicates a drain contact and 510 denotes an element isolating insulating film.
Generally, writing is effected by applying a voltage of 6 to 7 V to the drain diffused layer 508 and a high voltage of nearly 12 V to the control gate electrode 505. This causes hot electrons generated by avalanche breakdown near the drain to be injected into the floating gate 503 via the gate insulating film 502. As a result, the threshold value of the memory cell rises, completing the write operation.
Erasing is performed by placing the control gate 505 at the ground voltage and the drain portion 508 in an open state, and applying a high voltage to the source portion 507 to discharge the electrons injected into the floating gate 503 by a method called the Fowler Nordheim tunneling, thereby lowering the threshold value of the memory cell.
One known method of controlling the writing or erasing operation as mentioned above is a method called a command control system in which the data in the memory cells are controlled by selecting and executing an operation mode according to the signal from an external microprocessor (MPU) or the like.
In the case of the command control system, the chip basically comprises a section for receiving a control signal externally supplied, a section for deriving a command from the signal, and a section for writing, reading, or erasing data into or from the memory cells. The configuration of a conventional chip using this system will be described with reference to a block diagram shown in FIG. 3.
The chip of FIG. 3 comprises these blocks: they are an address buffer circuit 1, an address latch circuit 2, a column decoder circuit 3, a row decoder circuit 4, a column gate 5, a memory cell array 6, a command register circuit 7, a control circuit 8, a sense amplifier circuit 9, a data latch circuit 10, an input/output buffer circuit 11, a write voltage circuit 12, and an erase voltage circuit 13. The direction of the arrow going in and out of each block represents the exchange of signals.
The operation of writing data in a memory cell of the memory cell array 6 according to a command will be explained, referring to FIGS. 3 to 5. FIG. 4 is a circuit diagram of the command register circuit 7 of FIG. 3. FIG. 5 shows waveforms related to the operation of the command register 7.
First, a specific write command has been transferred from external signals I/O.sub.0 to I/O.sub.n to the input/output buffer circuit 11, and the external control signals /CE (/ means an inverted signal) and /WE externally supplied (e.g., an MPU) are at a high level (hereinafter, abbreviated as "H"). In this state, the chip is in a waiting state.
When the external control signals /CE and /WE go from a high to a low level (hereinafter, abbreviated as "L"), the inside of the chip becomes active. Then, according to the specific write command, given ones of signals D.sub.0 C to D.sub.n C and/D.sub.0 C to/D.sub.n C are transferred from the input/output buffer circuit 11 to the command register circuit 7.
Of the internal control signals WES1 and /WES1 obtained by shaping the external control signal /WE, WES1 is "H" and /WES1 is "L".
Part of the operation of the command register circuit 7 as well as a writing operation will be described with reference to FIG. 4. Accordingly, FIG. 4 is treated as a write command register. A NAND circuit 14, using given ones of signals D.sub.0 C to D.sub.n C and/D.sub.0 C to D.sub.n C as gate inputs, has only "H" ones of signals D.sub.0 C to D.sub.n C and/D.sub.0 C to/D.sub.n C connected to the gate upon arrival of the write command. For instance, if a combination of "H" external signal IO.sub.0, "L" IO.sub.1, "L" IO.sub.2, and "H" IO.sub.3 represents the write command, only gate input signals D.sub.0 C, /D.sub.1 C, /D.sub.2 C, and D.sub.3 C are connected to the gate of the NAND circuit 14. Namely, the NAND circuit 14 is constructed so that all of its gate input signals may not be "H" even if a command other than the write command is externally supplied.
Therefore, when a write command is supplied, the output node (hereinafter, abbreviated as N) N1 of the NAND circuit 14 goes to a "L" level. Because node BB is "L" at the start of power supply, or in the initial state, the output N2 of a NOR circuit 15 in the next stage goes "H". A p-channel MOS transistor TR1 one end and the other end of which are connected to N2 and N3, respectively, and whose gate is supplied with signal /WES1, and an n-channel MOS transistor TR5 one end and the other end of which are connected to N2 and N3 respectively, and whose gate is supplied with signal WES1 becomes conductive, and N3 goes "H" as N2 does.
The output N4 of an inverter circuit using the N3 as an gate input goes "L", causing the output N5 of an inverter circuit using N4 as an gate input to go to a "H" level. At this time, p-channel MOS transistors TR2 and TR3 and n-channel MOS transistors TR6 and TR7 are nonconductive. However, because p-channel MOS transistors TR2 and TR3 and n-channel MOS transistors TR6 and TR7 were conductive in the initial state, the signal at N6 is "L", that at N7 is "H". As a result, the output N8 of an inverter circuit using N7 as an gate input is at a "L" level. Consequently, the output N9 of an inverter circuit using N8 as an gate input is "H", placing the output node BB of an inverter circuit using N9 as an gate input at a low level.
Since the arrangement of a subsequent-stage register connected to N8 is the same as that mentioned above, its explanation will be omitted. Here, because the signal at N8 is "L", that at N10 is "L", which places N11 at a "H" level, thus making the signal at N12 "L". This places N13 at a "L" level, which brings N14 to a "H" level, thus making the signal at N15 "L". Therefore, the output N16 of an inverter circuit using N15 as an gate input goes "H", thereby making the program control signal PC passing through an inverter circuit goes "L".
Next, when external control signals /CE and /WE go from "L" to "H", transistors TR1 and TR5 become nonconductive this time. In contrast, since transistors TR2, TR3, TR6, and TR7 become conductive, the signal at N6 goes "H" and that at N7 goes "L", with the result that the output N8 of the inverter circuit using N7 as an gate input goes "H" . This causes the signal at N9 to go "L" and signal BB to go "H", which resets the output N2 of a NOR circuit 15 using signal BB as an gate input to a "L" level. Because a p-channel MOS transistor TR9 and an n-channel MOS transistor TR13 one end of each of which is connected to the "H" signal at N8 are still nonconductive, they have no effect on the next-stage node. What has been described up to this point is associated with a first step of the command, in which the write mode is set up.
Next, when external control signals /CE and /WE go from "H" to "L" again, TR9 and TR13 becomes conductive, making the signal at N10 go from "L" to "H", with the result that the output N11 of an inverter circuit using N10 as an gate input goes "L" and the output N12 of an inverter circuit using N11 as an gate input goes "H". However, because the p-channel MOS transistor TR11 and n-channel MOS transistor TR15 are still nonconductive, the change is not transmitted to the next stage.
Then, when external control signals /CE and /WE go from "L" to "H" again, TR11 and TR15 become conductive, which permits a "H" level at N13 to be transmitted to N13, thus causing the signal at N13 to go from "L" to "H", with the result that the output N14 of an inverter circuit using N13 as an gate input goes "L" and the output N15 of an inverter circuit using N14 as an gate input goes "H". This makes the signal at N16 go "L", thus making register circuit output signal PC go "H". This change is transmitted from the command register circuit 7 to the writing system of the control circuit 8, the address latch circuit 2, and the data latch circuit 10.
what has been described up to this point is associated with a second step of the command. The register is constructed so that each time external control signals /CE and /WE go "H", then "L", again "H", the signal is transmitted sequentially inside the command register 7. In parallel with the first and second steps of the command explained in the above command register circuit, the address and writing data are also supplied.
Specifically, when external control signals /CE and /WE are "H" in the second step of the command, external signals A.sub.0 to A.sub.n corresponding to a given address are transferred to the address buffer circuit 1. At the same time, the data to be written into a memory cell is set according to external signals I/O.sub.0 to I/O.sub.n, and is transferred to the input/output buffer circuit 11. At this time, to write data "0" (the state in which the threshold is high) in a memory cell, a "0" ("L") level is set for I/O.sub.0 to I/O.sub.n. Conversely, to write data "1", a "1" ("H" ) level is set for I/O.sub.0 to I/O.sub.n.
Then, the change of external control signals /CE and /WE from "H" to "L" activates the address buffer circuit 1 and the input/output buffer circuit 11, allowing the selected address data and writing data to be transferred to the latch circuits 2 and 10, respectively. According to these sets of data, the latch circuits select the column decoder circuit 3, column gate 5, and row decoder circuit 4. On the basis of the selected column line and row line (control gates), a memory cell in the memory cell array 6 is selected when external control signals /CE and /WE go "H", this starts the command write mode, which permits the control circuit 8 to output a "H" activating signal PRO, thereby activating the write voltage circuit 12. In this state, a write/erase power supply VPP is externally supplied to the chip, and a high voltage SW is applied to the selected column line and row line. With the voltages thus applied, a given data item transferred form the data latch circuit 10 is written into the memory cell.
In this way, the change of external control signals /CE from "H" through "L" to "H" completes a single step of the command. Specifically, in this case, in the first step of the command, the write mode is set up, and in the second step, the address data and the memory cell data are taken in, and then the write mode is started, which allows the data to be written in the selected memory cell.
To erase the data in the memory cell, a similar command control system is used. In this case, too, a specific erase command is previously transferred to the input/output buffer circuit 11 by external signals I/O.sub.0 to I/O.sub.n. Then, an erase command register (not shown), which has the same arrangement as that of the write command register circuit of FIG. 4, sets up the erase mode in the first step of the command as explained in the write mode. In the second step of the command, the source of the memory cell to be erased from is selected, and the control circuit 8 is activated by the erase command register circuit output signal EC. The control circuit 8 outputs a "H" activating signal ERA, which activates the erase voltage circuit 13. In this state, the external write/erase power supply VPP is supplied to the chip. This enables an erase high voltage VSO to be applied to the source connected to the memory cell array 6, thereby erasing the data in the memory cell.
Similarly, to read the data from the memory cell, the data in the memory cell at the address selected by the column line and the row line corresponding to input signals A.sub.0 to A.sub.n, which are transferred to these column and row lines via the address buffer circuit 1, address latch circuit 2, column decoder circuit 3, column gate 5, and row decoder circuit 4, is outputted via the sense amplifier circuit 9, the data latch circuit 10, and the input/output buffer circuit 11.
However, when the chip is externally controlled by, for example, the above-described command control system, there is a possibility that a write or an erase command will be taken in erroneously due to power supply noise inside and outside the chip or command-caused noise, which results in a malfunction, eventually leading to the danger of destroying the data in the memory cell. When the memory cell array 6 is divided into blocks, a malfunction can take place in each selected block.